The present invention relates to an IC testing method which enables a function test and a leak current test to be performed in a brief time interval when conducting a function test and a direct current (DC) test for a semiconductor device such as a memory formed by a semiconductor integrated circuit, and to an IC testing apparatus which employs the method.
Heretofore, an IC testing apparatus which tests a semiconductor device such as a memory performs a function test which determines whether or not the function of the semiconductor device is normally operating and a direct current test which determines whether or not respective terminals of the semiconductor device exhibit predetermined direct current characteristics. The IC testing apparatus determines an IC which proved to be normal in both the function test and the DC test to be an acceptable product.
FIG. 3 shows a schematic arrangement of an IC testing apparatus. In this Figure, character TES designates the entire IC testing apparatus. The IC testing apparatus TES is internally categorized into a main controller MAIN, a function tester 100 and a DC tester 200.
The main controller MAIN comprises a computer system, and controls the function tester 100 and the DC tester 200 through a bus line BUS. The function tester 100 comprises a pattern generator 102, a timing generator 104 and function test units 106A, 106B, . . . , 106N.
The function test units 106A-106N are associated with respective terminals of an IC tinder test 300 so that switches S11-S1n, can be turned on and off to have the function test units 106A-106N connected with or disconnected from the respective terminals of the IC under test 300.
Thus the function test takes place by controlling the switches S11-S1n to their on conditions to have the function test units 106A-106N connected to the respective terminals of the IC under test 300 for applying test pattern signals to the respective terminals of the IC under test 300 to carry out the function test.
On the other hand, one or more DC testers 200 are provided for testing the terminals of the IC under test 300 (in the example shown in FIG. 3, the provision of the single DC tester 200 is shown). One or more DC testers 200 are arranged such that change-over switches S21-S2n are controlled to be on such that each DC tester 200 is connected to only one of the terminals on the IC under test 300 at a time, thus sequentially testing the DC characteristic of the specific terminals. Incidentally, 400 designates a controller which controls these switches S11-S1n and S21-S2n.
FIG. 4 shows an internal arrangement of one of the function test units, 106A, and the summary of the function test will be described. The function test unit 106A (the remaining function test units are similarly arranged) comprises a waveform formatter 11, a driver 12, a voltage comparator 13, a logical comparator 14 and a fault analysis memory 15.
The waveform formatter 11 receives test pattern data applied from the pattern generator 102 and produces a test pattern signal having an actual waveform. The timing generator 104 supplies a timing signal which defines the rise timing and the fall timing of the test pattern signal to the waveform formatter 11.
The test pattern signal delivered from the waveform formatter 11 is shaped by the driver 12 into a waveform of an amplitude having a given logical value, which is fed through the switch S11 to a given terminal on the IC under test 300 to store data in the IC under test 300. If this terminal is an I/O terminal (a combined input and output terminal), the terminal on the IC under test 300 is set into an input mode when inputting the test pattern signal, and is switched to an output mode at the time when a write operation is performed. Content stored in the IC under test 300 is read out when switched into the output mode, and is fed through the voltage comparator 13 to the logical comparator 14. Incidentally, when the voltage comparator 13 reads data delivered from the IC under test 300, the output terminal of the driver 12 is set up in its high impedance mode.
The voltage comparator 13 determines by comparison whether the logic signal read out from the IC under test 300 attains a normal voltage value. Thus, voltage comparator 13 determines whether or not L logic and H logic levels are present, for example, 0.8 volt or lower and 2.4 volt or higher, respectively, and for a signal having a voltage that is a normal logic value, the appropriate logic value is input to the logical comparator 14.
An expected value is input to the logical comparator 14 from the pattern generator 102, and is compared against the logic value which is input from the voltage comparator 13, thus detecting the occurrence of any non-coincidence. In the event a non-coincidence occurs, it is assumed that there exists a fault in a memory cell it an address where a write operation took place, the fault is stored in the fault analysis memory 15 at this address, and subsequent to the completion of the test, the number of faulty cells is counted by reading out the fault analysis memory 15 to determine whether or not it is possible to salvage the IC under test 300.
FIG. 5 shows an example of the arrangement of the DC tester 200. The arrangement shown is one which is used when the DC tester 200 operates in a voltage applied current measuring mode. A voltage VL or VH is applied to a non-inverting input terminal of an operational amplifier 16 in response to a logic value from a DA converter 17 that is applied to a terminal on the IC under test 300.
A current detecting resistor R1 is connected between the output terminal of the operational amplifier 16 and a current output terminal TI, a switch Sa2 is connected between the current output terminal TI and a sensing point SEN, a protective resistor R3 is connected between the current output terminal TI and a voltage detecting terminal TV, and the voltage detecting terminal TV is connected to the sensing point SEN through a switch Sa1. The sensing point SEN is connected through a change-over switch S21 to a terminal on the IC tinder test 300. An inverting input terminal of the operational amplifier 16 is connected to the voltage detecting terminal TV.
Incidentally, a switch Sb connected in shunt with the current detecting resistor R1 represents a range change-over switch which changes the current measuring range. By controlling the switch Sb on, a resistor R2 of a smaller resistance, which allows a measurement of a high current (a current in the output mode of the IC under test 300), is connected in circuit, thus changing over to a high current measuring range.
With this arrangement of the DC tester 200, the voltage VL or VH, applied to the non-inverting input terminal of the operational amplifier 16 from the DA converter 17 is applied to a terminal on the IC under test 300 by controlling the switches Sa1,Sa2 and the change-over switch S21 to on conditions.
Specifically, since the operational amplifier 16 operates to make voltages at the non-inverting and the inverting input terminal equal to each other, if VL, for example, is applied to the non-inverting input terminal of the operational amplifier 16, the output voltage is controlled so that the voltage at the inverting input terminal (equal to the voltage at the voltage detecting terminal TV) also assumes VL. Accordingly, the voltage VL or VH, is applied to a terminal on the IC under test 300.
In the DC test mode, each terminal Pi of the IC under test 300 is set up in its input mode as shown in FIG. 6. By measuring a current which passes through the current detecting resistor R1 under the condition that V1 (a voltage providing an L logic) or VH (a voltage providing an H logic) is applied to the terminal Pi, respective leak currents IRek1 and IRek2 of active elements Q1 and Q2 connected to the terminal Pi can be measured. Subtractor circuit 18 derives a voltage developed across the current detecting resistor R1, and AD converter 10 applies an AD conversion to the voltage obtained by the subtraction circuit 18 to deliver a digital value.
When measuring the leak currents IRek1, IRek2 passing through each input terminal of IC under test 300, change-over switch Sb is turned off, thus measuring a voltage developed across the current detecting resistor R1 having a relatively high resistance on the order of 100 kxcexa9 and measuring the leak currents IRek1 and IRek2 passing through each input terminal of the IC under test 300. Incidentally, the protective resistor R3 is formed by a resistor having a relatively small resistance (on the order of several 10""s xcexa9), thus securing a closed feedback loop to the inverting input terminal of the operational amplifier 16 if the switches Sa1 and Sa2 are simultaneously controlled to be off during the actual operation. Resistor R3 thus protects the operational amplifier 16 by preventing an operation that would cause the operational amplifier 16 to saturate.
From the foregoing summary, the function test and the DC test in the IC testing apparatus should be understood. It is to be noted that heretofore, the function test and the DC test mentioned above have been performed in different time intervals, that is to say, after one of the tests is performed, the other test is performed. In particular, in the DC test, it is necessary to provide a control which changes the change-over switches S21, S22. . . S2n and to provide a control which changes the switches S11-S1n shown in FIG. 3. The manner of these controls will be described with reference to FIG. 7.
The function test is performed under the condition that the switches Sal, Sa2 and the change-over switches S21-S2n. shown in FIG. 3 are all changed to off conditions to disconnect the DC tester 200 from the terminals on the IC under test 300 while the switches S11-S1n are all controlled to on conditions. Thus, because the output impedance of the DC tester 200 is relatively low on the order of several xcexa9""s, if the DC tester 200 is electrically connected as a load on the function tester 100 during the function test, the waveform of a test pattern signal which is fed from the function tester 100 to the IC under test 300 is degraded. This degradation prevents the function test from being performed in a normal manner.
For this reason, the function test is performed by controlling all of the change-over switches S21-S2n, and the switches Sa1, Sa2 to off conditions, which controls the DC tester 200 so that it is not connected to any terminal on the IC under test 300.
On the other hand, when performing the DC test, switches S11-S1n are all initially controlled to on conditions, which connects the function test units 106A-106N to all the terminals on the IC under test 300. Under this condition, an initializing pattern for conducting the DC test is applied to the IC under test 300.
Specifically, if a terminal which is subject to the DC test is an I/O terminal, an initializing pattern (see FIG. 7C), which sets up an input mode as the mode for the terminal, is input from the function tester 100. After the input mode is set up at the terminal which is subject to the DC test, that terminal exercises a control which disconnects the function test units 106A-106N from all the terminals on the IC under test 300.
Under this condition, the change-over switch S21 is controlled to be on for performing the DC test. The DC test measures the leak currents IRek1 and IRek2 (see FIG. 6) passing through the terminal under the condition that respective logic values of either H logic or L logic are applied to the terminals on the IC under test 300. If the leak current values are equal to or less than values which are previously predetermined, acceptability is determined, while if they are equal to or greater than the values, fault is determined.
In this manner, the DC test is performed for each terminal, and hence there is required, for each terminal tested, an interval Tpi (see FIG. 7D) equal to the sum of an interval TSW1 during which the switches S11-S1n are controlled on and off in order to apply the initializing pattern and an interval TSW2 during which the change-over switches S21-S2a are controlled in a switching manner. The interval TSW1 for applying the initializing pattern and the interval TSW2 for controlling the change-over switches S21-S2n correspond to a time interval (several ms) for changing the switches (relays), and even if the interval T1M (FIG. 7E) for measuring the current is short, the total interval Tpi is relatively long. Accordingly, if a switching control of the switches S11-S1n and the change-over switches S21-S2n is executed for every terminal, there results an inconvenience that the DC test requires a long period of time. This hinders the testing of large quantities of IC""s.
It is an object of the invention to propose an IC testing method capable of testing quantities of IC""s in a brief interval by reducing the testing interval of an IC, and an IC testing apparatus which utilizes the testing method.
The invention is characterized by an arrangement which allows the DC tester to remain connected to a terminal on an IC under test even during the function test, which is enabled by connecting the DC tester to a terminal on the IC under test through a resistor such that the connection of the resistor prevents the DC tester from presenting a significant load as viewed from the function tester.
With this arrangement, there is proposed an IC testing method which permits the DC test to be executed by controlling the output terminal of a driver of the function tester to be put into a high impedance mode even during the function test, thus dispensing with the need for a switch control to disconnect the function tester during the time the DC test is being executed and thus allowing an execution of a leak test during the interval for the functions test.
Thus, with the IC testing method according to the invention, the leak test for a DC test item is completed at a time coincident with the end of the function test, thus eliminating the need for a special time interval to conduct the leak test. Consequently, there is obtained an advantage that the length of time required for the test can be significantly reduced.
In addition, the present invention proposes an IC testing apparatus which utilizes the IC testing method mentioned above.
An IC testing apparatus according to the invention comprises a function tester for executing the function test of an IC under test by applying a test pattern signal to each terminal on the IC under test from a driver which is capable of setting up a status of an output terminal thereof in a high impedance mode;
a DC tester for measuring a leak current passing through each terminal on an IC under test under a condition that a given voltage is applied to each terminal on the IC under test;
a resistor connected between the sensing point of the DC tester and the terminal on the IC under test;
first control means for causing a given voltage to be delivered to the sensing point of the DC tester during the execution of the function test by the function tester;
second control means for controlling the output terminal of the driver of the function tester in a high impedance mode at the time a control operation by the first control means is completed;
and current measuring means for measuring a leak current passing through a terminal of the IC under test under a condition that the output terminal of the driver is controlled in a high impedance mode.
With the IC testing apparatus according to the invention, there is no need to disconnect the function tester and the DC tester from each other during the execution of the function test and also during the execution of the DC test. Accordingly, the DC test can be executed during the execution of the function test without a need for the time to change the switch.
As a consequence, if the DC test is executed during the execution of the function test, the DC test is dispersed in a compound form in the function test, and there is obtained an advantage that a length of time for the compounded test cannot be significantly longer than the length of time required for the inherent function test, thus allowing the function test and a leak test to be completed within a brief interval.